The present invention is related generally to clocked electronic circuits and more particularly to a credit for correcting the duty cycle of a clock signal and to circuits and methods employing the duty cycle correction circuit.
The need for synchronized clock signals between two or more communicating circuits or components is well known. In many applications, it is desirable that the duty cycle of the clock signal be maintained at 50%. Most clock generation circuits and clock signal amplifier and buffer circuits introduce some level of error from the desired 50% duty cycle, however. Prior art approaches to duty cycle correction have typically employed the use of a large filter capacitor. An example is U.S. Pat. No. 5,572,158 to Lee et al., wherein a large capacitor is employed to slew limit the clock signal. Zbinden, U.S. Pat. No. 4,527,075, uses low pass filters to generate DC levels proportionate to the deviation from the desired duty cycle, which DC levels are used to generate a feedback correction signal. In U.S. Pat. No. 5,757,218, Blum uses a feedback circuit to adjust the delay imposed by a clock signal chopping circuit. Such approaches are disadvantageous, however, because the large physical size of the capacitor is undesirable and/or because such solutions have a long response time or are inefficient.
In a first aspect, the present invention provides a duty cycle correction circuit for receiving at a pair of differential inputs an uncorrected differential clock signal having a sinusoidal characteristic, and outputting at a pair of differential outputs a corrected differential square wave clock signal. The circuit includes a first differential pair of transistors coupled to a first current source at one of their sources and drains, coupled by the other of their sources and drains to a differential comparator, the connection nodes of the first differential pair of transistors and of the comparator comprising a pair of internal nodes. The differential comparator is responsive to crossovers in current at the pair of internal nodes to provide a differential square wave output signal at the pair of differential outputs. The first differential pair of transistors is coupled by their gates to the pair of differential inputs. The circuit also includes a second differential pair of transistors coupled to a second current source at one of their sources and drains, and is coupled to the pair of internal nodes at the other of their sources and drains. The second differential pair of transistors is adapted to receive differential control signals at their gates. A duty cycle correction feedback circuit is provided, having a pair of feedback inputs coupled to the pair of differential outputs and having a pair of feedback outputs providing the differential control signals. The duty cycle correction feedback circuit includes a capacitor coupled across the pair of feedback outputs, as well as circuitry for adding or subtracting charge to one plate of the capacitor in accordance with the corrected differential clock signal so as to control a differential voltage across the capacitor. The circuit includes an amplifier adapted to amplify and invert the differential voltage across the capacitor to provide the differential control signals at the pair of feedback outputs, the differential control signals having a level adapted to control current provided to the pair of internal nodes by the second amplifier so as to control the timing of the crossover of differential current at the pair of summing nodes to provide the desired duty cycle correction. In another aspect, the invention provides a method for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage. The correction differential current is provided to the pair of summing nodes to produce a corrected differential current as the sum of the uncorrected differential current and the correction differential current so as to control the timing of the crossover of the corrected differential current at the pair of summing nodes to provide duty cycle correction. Finally, the corrected differential square wave clock signal is provided by generating a differential square wave voltage corresponding to the corrected differential current.
An object of the present invention is to provide a fast and efficient duty cycle correction circuit.
A further object of the present invention is to provide an efficient duty cycle correction circuit that can be realized using conventional semiconductor manufacturing processes, or using discrete components.
Yet another object of the present invention is to provide for data transmissions circuits and devices that provide for a high degree of jitter tolerance using clock signal duty cycle correction.